SK Hynix has developed 4D NAND flash chip that is more advanced than the conventional 3D NAND memory chip. The South Korean semiconductor giant announced Sunday that it developed for the first time in the world a 96-layer 512-gigabit TLC (triple level cell) 4D NAND flash, by incorporating PUC technology into Charge Trap Flash (CTF) structure, which is commonly applied to 3D NAND flash chips.
CTF is a technology that enhances performance and productivity by minimizing interference between cells, while Peri Under Cell is technology for placing the peripheral circuit that controls the cells at the bottom of data storage cells. Most chipmakers adopt CTF for their 3D NAND flash chips, but SK Hynix is the first in the world to have applied PUC to CTF.
Through this technique, the chip size of the 4D NAND flash has been reduced by more than 30 percent from a 72-layer 3D NAND flash, while yield per wafer has increased by 1.5 times. The new 4D chip can substitute two 256 gigabit 3D NAND, cutting production costs. The new chip provides 30 percent higher write and 25 percent higher read performance when compared with the 72-layer product, while the data volume that can be concurrently processed by the chip is among the largest in the industry.
SK Hynix will introduce 1 terabit-capacity solid stat e drive (SSD) equipped with the new 4D NAND flash chip for consumers by the end of this year. The company also plans to switch 72-layer SSD products for corporate clients with 96-layer SSD devices next year.
Dong-Jin Shin firstname.lastname@example.org